The present invention pertains to the field of electrical systems. More specifically, the present invention pertains to a structure and method thereof for conducting electricity between devices, such as between conductive layers in a multilayer printed wiring board.
As is well known in the art, a packaged integrated circuit typically consists of an integrated circuit die encapsulated in a protective material such as ceramic or plastic. The packaged integrated circuit is attached to an underlying circuit board by soldering or using some type of electrical connector. The attachment mechanism is used to power and ground these devices as well as to pass address signals, data signals, control signals and other electrical signals from the integrated circuit package to the printed wiring board, enabling electrical signals to flow between various devices.
In one instance, multilayer printed wiring boards are used, where multiple conductive layers are laminated together, separated by an insulating material (e.g., a dielectric material). In the prior art, the signal path on one layer is continued on another layer using a drilled hole which has been metallized. These metallized drilled holes are commonly known as vias. In one type of connection, an electrical component is soldered to the surface of a printed wiring board containing etched traces. These traces provide an electrical path for signals. The trace proceeds along the circuit board and is connected to a via that, for example, is coated with a conductive material. The coated via extends into the internal structure of the printed wiring board where it may connect to an etched trace on an internal layer, forming a continuous electrical path on two or more layers. In another type of connection, the electrical connector of the device is electrically coupled directly to the via. In either case, the two devices are connected by an electrically conductive path using one or more vias and two or more layers.
In another instance, on a smaller scale that is analogous to the above, integrated circuit substrates in a device can be Layered one on top of another, separated by an insulating material. Vias can be used in a manner similar to the above to establish an electrically conductive path between layers of the substrate.
Prior Art FIG. 1 illustrates the use of vias with, for example, a plurality of layers containing electrically conductive paths that are laminated into a unified structure 150. Each layer (e.g., conductive layers 105) is separated from a neighboring layer by insulating layer 100. Insulating layer 100 is comprised of a dielectric material (polymers or various other materials known in the art). Conductive layers 105 and insulating layer 100 typify the conductive and insulating layers in structure 150.
Structure 150 includes vias 110, 120 and 130. Via 110 is a xe2x80x9cblind viaxe2x80x9d extending from an external conductive layer through two insulating layers to an internal conductive layer. Via 120 is a blind via extending from an external conductive layer through one insulating layer to an internal conductive layer. Via 130 is a xe2x80x9cburied viaxe2x80x9d connecting two internal conductive layers through an insulating layer.
A frequently used type of prior art electrical connector is a ball grid array (BGA). In a BGA connector, a plurality of electrically conductive balls are used to transfer electrical signals from one location (or device) to another. For example, a BGA connector can be used to send or receive signals between an integrated circuit die and an underlying printed circuit board. The BGA is electrically coupled to the various input and output pads of the integrated circuit. The BGA is also electrically coupled to landing pads on the printed circuit board, and the landing pads are in turn electrically coupled to a via. While there may be more details associated with the implementation of a BGA and vias, it is appreciated that those details are known in the art.
Currently, the conductive balls in a large format BGA are typically arranged with a pitch of approximately 1 millimeter (or about 40 mils). However, as the complexity and input/output (I/O) capability of integrated circuits grow, the number of conductive balls in a BGA will also need to grow commensurately, necessitating a reduction in pitch. Accordingly, a pitch on the order of 0.8 mm or perhaps even 0.65 mm may be required in order to accommodate the next generation of devices and beyond.
As the number of conductive balls increase and they become more densely packed, a problem is introduced regarding how to escape the footprint made by the BGA. That is, if there are a large number of conductive balls (perhaps on the order of 2000), and correspondingly a large number of traces coupled with the conductive balls, then it will become difficult to find room to route the traces on the printed circuit boards.
Consequently, the number of vias will also need to be increased, which in turn can introduce a number of other disadvantages. First, the increasing number of vias can consume a significant amount of the already limited space on the printed circuit boards, and so it is desirable to reduce the size of vias (that is, their diameter) if possible. Also, it is desirable to reduce the size of vias in order to accommodate the reduced pitch of, for example, a BGA. On the other hand, there are physical and practical limits which preclude formation of vias less than approximately 75 micrometers (microns) in diameter, using existing technology.
Accordingly, what is needed is a solution that can accommodate the increasing complexity of next-generation miniaturized devices such as integrated circuits without increasing, and preferably by decreasing, the amount of space consumed on circuit boards by vias. What is also needed is a solution that addresses the above needs and can reduce the difficulties associated with manufacturing smaller and smaller vias. The present invention provides a novel solution to the above needs.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
In one embodiment, the present invention pertains to a structure and method thereof for providing an electrically conductive path between a first conductive point and a second conductive point on adjacent layers separated by an insulating layer. The present invention can accommodate the increasing complexity of next-generation miniaturized devices such as integrated circuits without increasing the amount of space consumed on circuit boards by vias. In accordance with the present invention, the size (e.g., diameter) of the conductive path can be significantly reduced.
In the present embodiment of the present invention, the structure includes an insulating material disposed between the first conductive point and the second conductive point. A dipole material is homogeneously distributed within the insulating material. The dipole material is comprised of randomly oriented magnetic particles. During the manufacturing process, the magnetic dipoles in a selected localized region of the insulating material are aligned to form an electrically conductive path between the first conductive point and the second conductive point through the insulating material.
In one embodiment, the present invention is implemented in a multi-layered application comprised of a plurality of layers containing conductive paths. The insulating material is disposed between each layer and a neighboring layer. An electrically conductive path is formed through the insulating material between neighboring layers, as described above, or between non-neighboring layers.
In one embodiment, the layers are conductive layers (e.g., an integrated circuit substrate) that, with the insulating material, form a semiconductor package having alternating conductive layers and insulating layers. In one embodiment, connection to the semiconductor package is made through an array of attachment points (e.g., ball grid array, etc.).
Therefore, the present invention allows an electrically conductive path to be formed through an insulating material without the need for a drilled or photo-defined hole (e.g., a via) in the insulating material. For example, in a semiconductor package, the conductive path formed in accordance with the present invention can be significantly smaller than a via formed with existing technology, preserving valuable real estate in the semiconductor package and also allowing a denser array of input/output attachment points on the semiconductor package.